As chip architectures grow increasingly complex, the importance of advanced packaging continues to rise, placing new demands on inspection and metrology. When multiple chips or chiplets are integrated into a compact space, their internal structures, interconnect integrity, and physical deformation must all be reliably inspected. ZEISS Semiconductor Manufacturing Technology (SMT) addresses these requirements with its ZEISS NLX and ZEISS DUNE systems.
ZEISS NLX enables clear visualization of the internal structures of modern chip packages without damaging the sample. For instance, chip manufacturers can use it to examine the connections between stacked chips and identify potential defects at an early stage. Designed for 300mm wafers, the system supports both new process development and high-volume production.
Wafer warpage is another critical challenge in complex manufacturing processes. ZEISS DUNE measures wafer surface topography and enables corrections for individual wafers. In this way, the system facilitates complex process steps—for example, by preventing yield loss in subsequent operations or preparing wafers for bonding processes.
"The next generation of semiconductor manufacturing will not rely on a single breakthrough technology; rather, it depends on the precise coordination of numerous, highly complex process steps. Close technical collaboration is essential, especially in key innovation markets like the United States. At ZEISS SMT, our deep expertise in optical systems and process control complements our new solutions for advanced packaging. Together, these capabilities help our customers bring future chip generations into production—reliably, efficiently, and at scale," says Christoph Hensche, President of ZEISS Semiconductor Manufacturing Optics and member of the ZEISS SMT management team.
Advanced packaging is just one part of ZEISS SMT’s comprehensive technology portfolio.
Photomask solutions represent a key focus area for ZEISS SMT and are vital for maintaining the stability of lithography processes. The ZEISS AIMS EUV 3.0 system allows for the inspection of photomasks under optical conditions similar to those found in wafer scanners, enabling the detection and assessment of critical defects before they can impact production. This system supports both Low-NA and High-NA EUV lithography and can triple mask inspection throughput; it is already being utilized by leading chip manufacturers. Meanwhile, the ZEISS MeRiT system enables the targeted repair of even the most minute defects on photomasks, providing a critical mask-processing step that complements the quality assessments performed by the AIMS EUV platform.
"As the demands of semiconductor manufacturing continue to rise, the importance of photomask quality has become increasingly prominent. Through the ZEISS AIMS® EUV 3.0 and other mask solutions, ZEISS SMT helps customers evaluate defects at an early stage and supports stable lithography processes. Working in close collaboration with our customers and partners also enables us to continuously refine these solutions to meet the specific requirements of next-generation chips," said Axel Christian, President of ZEISS North America.
